Michael,
IP/SOC
2005 (IP Based SoC Design) will be the 14th edition of the Working
conference on hot topics in the design world, focusing for the past
5 years on IP based SoC design and hold in the well known Silicon
and Alliance Nanometer Valley in the French Alps.
WORKING CONFERENCE
The areas of interest for the IP/SOC 2005 (IP Based SoC Design)
event includes (but not restricted to):
- Silicon and Software IP design and packaging
- Impact of Nano technology
- Foundries role in the IP business
- IP /SOC design flow, IP based ASIC platforms
- IP/SoC qualification, emulation and prototyping
- ESL for IP/SoC
- Internet/Intranet Catalog technology, web based collaborative
design, IP/SoC design data management
Similarly to the previous events, this working conference in 2005
will be partitioned into technical papers, panels and invited papers
with a balanced contribution from industrial and academic
participants. Panels on hot topics such as the impact of Nano
technology, verification challenge, IP business, ESL, ASIC platforms
are already planned for an exciting 2005 event. Please identify
yourself for participation to a session, a panel. New topics are
welcome, please contact us at ipsoc2005@design-reuse.com.
IP/SOC 2005 BEST PRIZES
Best IP/SoC Award 2004 will
be delivered under the sponsorship of ST Microelectronics both for
the best design and design methodology / tool contribution.
Best contributions and hottest events will be live on demand on
D&R web site for 6 months after the event
EXHIBITION In addition the "IP/SoC 2004 working
conference" has an exhibition attached, giving you the opportunity
to see the reality of a SOC connected world. The joint exciting
dedicated exhibition will allow you to meet the most advanced
suppliers and take the chance to see the last products of the best
vendors.
You can
book your space here.
PROGRAM COMMITTEE MEMBERS
- G. SAUCIER - Design And Reuse, France
- Technical Program Chair :
- H. KRUPNOVA - ST Microelectronics, France
- Industry / University representatives :
- Prof. K. ASADA - Tokyo University, Japan
- P. BLOUET - ST Microelectronics, France
- P. BRICAUD - Synopsys, France
- A. BRUENING - sci-worx GmbH, Germany
- T. DANIELS - LSI Logic, UK
- B. DE LOORE - Philips Semiconductors, The Netherlands
- N. DE MICHELI - Stanford Univ., USA
- S. DUTTA - Philips Semiconductors, USA
- P. DWORSKY - Synopsys, USA
- J. HAASE - Edacentrum, Germany
- J. HARDEE - CoWare, USA
- J. HILSBERG - IBM, SW
- J. VENABLE - Mentor Graphics, USA
- C. LENNARD - ARM, UK
- P. MAGARSHACK - ST Microelectronics, France
- S. MORI - IPTC, Japan
- H.N. NGUYEN - Bull, France
- T. PFIRSCH - Alcatel, Belgium
- K. REID - Cadence, UK
- M. ROBERT - LIRRM,University Montpellier, France
- Prof. W. ROSENSTIEL - FZI Karlsruhe University, Germany
- M. VELEV - School of Electrical and Computer Engineering at
the Georgia Institute of Technology, USA
- Prof. N. WEHN - University of Kaiserslautern , Germany
- H. VAN DER WILDT - H&A, USA
SUBMISSION PROCEDURE
You
can submit an electronic version of your executive summary (3 pages
approximately) in a Word, PDF or PostScript format using one of the
following methods :
1. By using the Online Submission Form
## RECOMMENDED ##
http://www.us.design-reuse.com/ipsoc2005/submit
2.
By sending an e-mail containing the paper title, yours names,the
name of the contact author, postal and e-mail address,telephone and
fax number, as specified in the online submission form to ipsoc2005@design-reuse.com.
All
the correspondence with authors will be handled by
e-mail.
Outstanding papers submitted or accepted in other
conferences will also be considered in this workshop. Please specify
it in your submission.
IMPORTANT DATES
| Deadline for submission of extended abstract |
September 26, 2005 |
| Notification of acceptance |
October 22, 2005 |
| Final Version of the manuscript |
November 12, 2005 |
Working Conference
|
December 7-8,
2005 |
LOCATION
Espace Congres du World Trade Center
5 place
Robert Schuman
38 000 Grenoble
FRANCE
IP/SOC CONFERENCE
ARCHIVES
The foils of previous years' "IP Based SoC
Design" events presentations are available online :
Note also that two hot panels as well as LSI Logic keynote
talk from Harmel Sangha that took place during IP SOC 2004 have been
sponsored to become the first live webcasts on D&R site, namely:
- KEYNOTE
TALK: "Platform ASICs & Serial interconnects - Way of
the future" By Harmel Sangha, Director, CoreWare
IP Marketing - LSI Logic,USA
- PANEL:
"What's the State of Verification IP ?" Moderated
by Michael Santarini, Sr. Editor, EDA and cores, EETimes
(brought to you by HDL Design House)
- PANEL:
"IP Business Models: Where is the value in IP?"
Moderated by Jim Tully, VP Semiconductors, Gartner Dataquest
(brought to you by Mentor Graphics)
- KEYNOTE
TALK: "What is or should be D&R role in the IP business"
By Gabriele Saucier, Chairman of the Board,
Design And Reuse, France
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